clkDivider.vhd
-- msTimer - Clock Divider (50 Mhz -> 1 Khz) library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity clkDiv is port( clk,rst: in std_logic; clkout: out std_logic); end clkDiv; architecture Behavioral of clkDiv is constant clk_1khz: std_logic_vector(22 downto 0) := "00000001100001101010000"; signal clkcnt: std_logic_vector(22 downto 0); begin process(clk,rst) begin if rst = '1' then clkcnt <= "00000000000000000000000"; elsif (clk'event and clk = '1') then if (clkcnt = clk_1khz) then clkcnt <= "00000000000000000000000"; clkout <= '1'; else clkcnt <= clkcnt + 1; clkout <= '0'; end if; end if; end process; end Behavioral;

Milisecond Precsion Timer by Patrick Kramer is licensed under a Creative Commons Attribution-Noncommercial-Share Alike 3.0 United States License.

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