ssegDecoder.vhd

-- msTimer - 7seg Decoder

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity sevenSegmentDecoder is
port(    dp:        in        std_logic;
        number:    in     std_logic_vector(3 downto 0);
        sseg:        out     std_logic_vector(7 downto 0));
end sevenSegmentDecoder;

architecture Behavioral of sevenSegmentDecoder is
begin

    with number select
        sseg(6 downto 0) <=
            "1000000" when "0000", -- 0
            "1111001" when "0001", -- 1
            "0100100" when "0010", -- 2
            "0110000" when "0011", -- 3
            "0011001" when "0100", -- 4
            "0010010" when "0101", -- 5
            "0000010" when "0110", -- 6
            "1111000" when "0111", -- 7
            "0000000" when "1000", -- 8
            "0011000" when "1001", -- 9
            "0001000" when "1010", -- A
            "1100000" when "1011", -- B
            "0100001" when "1100", -- C
            "1000010" when "1101", -- D
            "0110000" when "1110", -- E
            "0111000" when others; -- F

    sseg(7) <= dp;

end Behavioral;

Creative Commons License
Milisecond Precsion Timer by Patrick Kramer is licensed under a Creative Commons Attribution-Noncommercial-Share Alike 3.0 United States License.

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