The specifications for this design was to create a 1ms precision timer with start, stop and increment features. I implemented a Finite State Machine (FSM) to use the start, stop and increment logic to control the decade counter by enabling and disabling them accordingly (I cover this later in the article). I also needed to multiplex the four separate seven segment displays; this was done using a 2-bit counter and scanning across the anodes to enable and draw each display independently. This way all four segments can be displayed effectively at once. It’s actually updated at 1/4 the input frequency, which in this case is 1 kHz; therefore the refresh rate of the seven segment display is 250 Hz.

My personal preference is to write behavioral VHDL modules and then put them together using a schematic. This not only makes it very simple to put a design together but it assists with troubleshooting problems with the circuit. For example, the AND gates placed in front of the clock-enable (cen) to remove a state ambiguity that occurs when the parent counters value is zero. As it so happens this issue effects three of the four counters (since they have parent counters); copying the fix to the other counters was a simple task.

The FSM used to control the timer was modeled after this state diagram. The initial state [s0] simply waits for user input to either increment the timer by 1ms [s2] or start the timer [s1]. The continuous run state [s1] simply enables the counters until stop is pushed. The increment trigger [s2] enables the counters for 1 clock cycle (1ms) then goes to the increment hold state [s3] until the user releases the increment button. This ensures that the increment only increases the clock forward by 1ms per push of the button.

Source Code:

• FSM.vhd
• ssegDecoder.vhd
• fourByFourMux.vhd
• decadeCounter.vhd
• clkDivider.vhd
• twoBitCounter.vhd
• anodeDecoder.vhd