FSM.vhd
-- msTimer - Finite State Machine library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity FSM is port (clk, rst: in std_logic; start,stop,inc: in std_logic; cen: out std_logic); end FSM; architecture Behavioral of FSM is type state is (s0,s1,s2,s3); signal state_current, state_next: state; begin -- State Register Controller process(clk,rst) begin if(rst = '1') then state_current <= s0; elsif (clk'event and clk = '1') then state_current <= state_next; end if; end process; -- Next State Logic process(state_current,start,stop,inc) begin case state_current is -- Reset State when s0 => if start = '1' then state_next <= s1; elsif start = '0' and inc = '1' then state_next <= s2; else state_next <= s0; end if; -- Timer Loop when s1 => if stop = '1' and start = '0' then state_next <= s0; else state_next <= s1; end if; -- Increment Trigger when s2 => state_next <= s3; -- Increment Hold when s3 => if inc = '1' then state_next <= s3; else state_next <= s0; end if; end case; end process; --Output Logic process(state_current) begin case state_current is --Timer loop and Increment Trigger when s1 | s2 => cen <= '1'; --Others when others => cen <= '0'; end case; end process; end Behavioral;

Milisecond Precsion Timer by Patrick Kramer is licensed under a Creative Commons Attribution-Noncommercial-Share Alike 3.0 United States License.

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